The present invention relates to semiconductor devices and more particularly to technology useful for semiconductor devices having SRAMs.
SRAM (Static Random Access Memory) is a kind of semiconductor memory which stores data using a flip-flop. Specifically, in an SRAM, data (1 or 0) is stored in two cross-coupled inverters comprised of four transistors. In addition, two access transistors are required for reading and writing, so in a typical SRAM, a memory cell is comprised of six transistors.
For example, Japanese Unexamined Patent Publication No. 2001-28401 discloses a semiconductor memory device having a static RAM memory cell comprised of six transistors (FIG. 1).
Also, Japanese Unexamined Patent Publication No. 2002-237539 discloses an SRAM memory cell (FIG. 32) in which NMOS transistors (N1 and N4) are formed in one P well region (PW0) and NMOS transistors (N2 and N3) are formed in the other P well region (PW1) with an N well region (NW) between the P well regions for the purpose of improving soft-error immunity.
Japanese Unexamined Patent Publication No. Hei7(1995)-7089 discloses an SRAM memory cell in which two divided driver NMOS transistors (transistor regions N1′, N1″, N2′, and N2″) are disposed over different P wells (FIG. 5) in order to improve soft-error immunity. In addition, in this SRAM cell, the gate direction of word line access transistors (NA1 and NB1) is perpendicular to the gate direction of the driver NMOS transistors (transistor regions N1′, N1″, N2′, and N2″).
Japanese Unexamined Patent Publication No. 2002-43441 discloses an SRAM memory cell in which an N channel MOS transistor (N1) with the main axis of a polysilicon wiring layer (PL11) as a gate electrode and an N channel MOS transistor (N′) with the fold-back axis of the polysilicon wiring layer (PL11) as a gate electrode are formed in a first P well region (PW1) (FIGS. 1 and 2 and paragraph [0062]).
Japanese Unexamined Patent Publication No. 2000-36543 discloses an SRAM memory cell in which two word lines (21a and 21b) are orthogonal to a p-type active region (13) around both ends thereof and parallel to each other and their length is short, or equivalent to about ½ bit, and common gate lines (22a and 22b) are orthogonal to both the p-type active region (13) and n-type active region (14) between the word lines (21a and 21b) and parallel to each other and equally spaced along with the word lines (21a and 21b) (FIG. 4). In the above explanation, the signs and numbers in parentheses are reference signs and drawing numbers which are used in the related art documents.